Semiconductor storage device, test method therefor, and test circuit therefor

ABSTRACT

A test method and a test circuit which enable operations to be checked when the time interval between a refresh operation and a read or write operation is forcibly reduced. Timings for a read or write operation in a normal operation mode and in a test mode are determined on the basis of an address transition detection circuit. A timing for a refresh operation in the normal operation mode is set on the basis of a normal refreshing pulse signal generated by a refresh pulse generating circuit in response to a timing signal generated by a timer circuit. A timing for a refresh operation in the test mode is set on the basis of a first testing refresh pulse generation signal generated by a first testing refresh pulse generating circuit in response to the address transition detection signal. By controlling a timing for generating the first testing refresh pulse generation signal, it is possible to generate a read or write operation and a refresh operation so that there is a predetermined time interval between these operations.

TECHNICAL FIELD

The present invention relates to a semiconductor memory device and amethod of testing the semiconductor memory device, and a test circuit.

BACKGROUND ART

SRAMs and DRAMs are the most typical of randomly accessiblesemiconductor memory devices. The SRAM generally operates faster thanthe DRAM. Further, simply by receiving a power supply and an inputtedaddress, an internal sequential circuit can operate in response to thischange in address to execute a read or write. The SRAM is thus operatedsimply by receiving a simple input waveform, in contrast to the DRAM. Itis thus possible to simplify a circuit that generates such an inputsignal waveform.

Further, the SRAM can retain data stored in memory cells withoutrefreshing, in contrast to the DRAM. Thus, advantageously, the SRAM canbe easily handled and requires only a small data retention current in astandby state because it does not require refreshing. Accordingly, theSRAM is used for various applications. However, since the SRAM generallyrequires six transistors per memory cell, the chip size becomes largeanyhow and it disadvantageously requires higher costs than the DRAM.

On the other hand, two addresses, that is, a row address and a columnaddress, must be separately provided to the DRAM. The DRAM furtherrequires a RAS (row address strobe) signal and a CAS (column addressstrobe) signal in order to specify the points in time at which theaddresses are loaded. The DRAM also requires a control circuit thatperiodically refreshes the memory cells. Consequently, the DRAM requiresmore complicated timing control than the SRAM.

Another problem with the DRAM is that the memory cells must be refreshedeven when there are no external accesses, which increases powerconsumption. However, a DRAM memory cell can be composed of onecapacitor and one transistor. Accordingly, it is relatively easy toincrease the capacity of the DRAM using a small chip size. Consequently,the DRAM is more inexpensive than the SRAM if these memories are used toconstruct respective semiconductor memory devices of the same storagecapacity.

SRAMs are now used for many of the semiconductor memory devices employedin portable equipment typified by cellylar phones. The reason will bedescribed below. First, old cellular phones comprise only simplefunctions and thus do not require a semiconductor memory device of alarge capacity. Second, the SRAM is easier to handle in terms of timingcontrol than the DRAM. Third, the SRAM requires only a small standbycurrent and consumes only low power and is thus suitable for cellularphones, for which it is desired to maximize continuous call time andcontinuous standby time.

Furthermore, cellular phones with a very large number of functions haveemerged and the following functions have been realized: an e-mailtransmitting function and a function to access various sites to acquireinformation on nearby restaurants and so on. Furthermore, very recentcellular phones comprise a function to access a WEB server on theInternet to simplify the contents of home pages and display it.Accordingly, like current desk top type personal computers, futurecellular phones are assumed to be able to access home pages or the likeon the Internet.

These functions cannot be realized simply by displaying texts as in thecase of conventional cellular phones. Graphic display is essential toprovision of various multimedia information to users. It is thusnecessary to temporarily store a large amount of data received through apublic network, in a semiconductor memory device in a cellular phone.That is, it is essential that semiconductor memory devices mounted infuture cellular phones have a large capacity as in the case of DRAMs.Further, portable equipment must absolutely be small and light, so thatincreasing the size or weight of the equipment itself must be avoidedeven with an increase in the capacity of the semiconductor memorydevice.

As described above, as a semiconductor memory device mounted in acellular phone, the SRAM is preferred in terms of the easiness withwhich it can be handled as well as power consumption. However, in termsof an increase in capacity, the DRAM is preferred. That is, the optimumsemiconductor memory device for this portable equipment has acombination of advantages of both SRAM and DRAM. As such a semiconductormemory device, a “pseudo SRAM” has been proposed which employs almostthe same memory cells as those of the DRAM but which can be apparentlyused in almost the same manner as that for the SRAM.

In contrast to the DRAM, the pseudo SRAM does not require the separateinputs of a row and column addresses and thus does not require timingsignals such as RAS and CAS. The pseudo SRAM can thus be operated simplyby receiving one address similarly to general-purpose SRAMs. By using asa trigger a chip enable signal corresponding to a clock of a clocksynchronous semiconductor memory device, the pseudo SRAM loads theaddress to execute a read or write.

However, the pseudo SRAM has a memory cell structure similar to that ofthe DRAM and must thus be periodically refreshed. Accordingly, somepseudo SRAMs use an internal timer to activate a refresh operation atfixed time intervals regardless of external control of operations. Thisrefresh operation is called a “self-refresh operation”. Timings forgenerating a self-refresh operation cannot be externally controlled.

On the other hand, some pseudo SRAMs operate asynchronously.Specifically, these pseudo SRAMs execute reads and writes in response toirregular changes in control or address signals. In these pseudo SRAMs,the self-refresh operation, controlled by the internal timer, isgenerated independently of read or write operations irregularlyperformed in response to externally inputted signals. Consequently, thetime intervals for these operations cannot be externally controlled.

Malfunction may occur if the self-refresh operation overlaps the read orwrite operation. For example, for the self-refresh operation, data to beretained may be destroyed. For the read or write operation, erroneousdata or addresses may be read or written.

To prevent such malfunction, the following measure is taken: forexample, if an operation is generated while another operation is beingperformed, the former operation is caused to stand by rather than beingstarted until the already activated operation is completed. That is, ifa read request is made during a self-refresh operation, a read operationis performed after the self-refresh operation has been completed, ratherthan being immediately performed.

However, the above measure may not ensure sufficient circuit operations.For example, if a timing for generating a self-refresh operation istemporarily close to a timing for generating a read or write operation,the operations may interfere with each other to cause malfunction. Thefollowing malfunction may occur: the interference between word lines, aninsufficient precharge resulting from short time intervals foroperations, or the disturbance of an operation by a pulse signalgenerated by another operation.

Accordingly, before products are shipped, it must be checked how theywill operate if the time interval between a self refresh operation and aread or write operation is short.

Conventional test modes for a refresh operation are described in, forexample, Japanese Laid-Open Patent Publication No. H1-125796 andJapanese Laid-Open Patent Publication (Kokai) No. H4-74379. However,these techniques only check the refresh operation itself and does notcheck how the device will operate if the time interval between a read orwrite operation and the refresh operation is short.

Thus, an object of the present invention is to provide a test methodthat can check how a device will operate if the time interval between aread or write operation and a refresh operation is forcibly short.

Another object of the present invention is to provide a semiconductormemory device that can check how a device will operate if the timeinterval between a read or write operation and a refresh operation isforcibly short.

Further, another object of the present invention is to provide a testcircuit that can check how a device will operate if the time intervalbetween a read or write operation and a refresh operation is short.

DISCLOSURE OF THE INVENTION

The present invention is provided to solve the above problems. Thepresent invention provides a method of controlling a semiconductormemory device having a plurality of memory cells to be refreshed,wherein a timing for a read or write operation in a normal operationmode and in a test operation mode is set using as a trigger anexternally inputted signal status change detection signal that detects achange in the status of an externally inputted signal, a timing for arefresh operation in the normal operation mode is set using as a triggera timing for generating a refresh control signal internally generated bythe semiconductor memory device, and a timing for the refresh operationin the test operation mode is set using the externally inputted signalstatus change detection signal as a trigger so that the time intervalbetween the timings for the refresh operation and for the read or writeoperation has an externally set value.

The externally inputted signal status change detection signal may be anaddress transition detection signal generated depending on at least oneof a timing for a change in an externally inputted address and a statustransition timing for a signal externally inputted that selectivelyactivates the semiconductor memory device. The signal selectivelyactivating the semiconductor memory device is, for example, a chipselect signal.

By using the status transition timing for the address transitiondetection signal as a trigger to generate a testing refresh pulse signala preset first predetermined time after the trigger, it is possible tocarry out tests under a first timing condition that the refreshoperation is started a first time interval after the read or writeoperation has been finished. The first time interval may be set to thesmallest value possible for a circuit configuration.

The address transition detection signal is composed of a one shot pulse.If an end-point edge of the one shot pulse is used as a trigger, thefirst predetermined time may be set on the basis of the sum of the timefor which a word line can be kept active and the first time interval, aswell as the delay time between preset signals.

The address transition detection signal is composed of a one shot pulse.If a start-point edge of the one shot pulse is used as a trigger, thefirst predetermined time may be set on the basis of the pulse width ofthe address transition detection signal, and the sum of the time forwhich a word line can be kept active and the first time interval, aswell as the delay time between the preset signals.

The address transition detection signal is composed of a one shot pulse.By using a start-point edge of the one shot pulse as a trigger togenerate a testing refresh pulse signal a preset second predeterminedtime after the trigger, it is possible to carry out tests under a secondtiming condition that the read or write operation is started a secondtime interval after the refresh operation has been finished. The secondtime interval may be set to the smallest value possible for the circuitconfiguration.

The second predetermined time may be set on the basis of the timebetween a rising edge of the address transition detection signal and arise in a word line for the read or write operation minus the sum of thetime corresponding to a word pulse width for the self-refresh operationand the second time interval, as well as the delay time between thepreset signals.

A test mode switch signal can be used to switch between the tests underthe first timing condition and the tests under the second timingcondition during the test operation mode.

The refresh operation in the test operation mode may be based on anaddress internally generated by the semiconductor memory device or theexternally inputted address.

Moreover, the present invention provides a method of testing asemiconductor memory device having a plurality of memory cells to berefreshed, wherein a timing for a refresh operation in a test operationmode is set using as a trigger an externally inputted signal statuschange detection signal that detects a change in the status of anexternally inputted signal so that the time interval between the timingsfor the refresh operation and for a read or write operation has anexternally set value.

The externally inputted signal status change detection signal may be anaddress transition detection signal generated depending on at least oneof a timing for a change in an externally inputted address and a statustransition timing for a signal that selectively activates thesemiconductor memory device. The signal selectively activating thesemiconductor memory device may be, for example, a chip select signal.

By using the status transition timing for the address transitiondetection signal as a trigger to generate a testing refresh pulse signala preset first predetermined time after the trigger, it is possible tocarry out tests under a first timing condition that the refreshoperation is started a first time interval after the read or writeoperation has been finished. The first time interval may be set to thesmallest value possible for a circuit configuration.

The address transition detection signal is composed of a one shot pulse.If an end-point edge of the one shot pulse is used as a trigger, thefirst predetermined time may be set on the basis of the sum of the timefor which a word line can be kept active and the first time interval aswell as the delay time between preset signals.

The address transition detection signal is composed of a one shot pulse.If a start-point edge of the one shot pulse is used as a trigger, thefirst predetermined time may be set on the basis of the pulse width ofthe address transition detection signal, and the sum of the time forwhich a word line can be kept active and the first time interval, aswell as the delay time between the preset signals.

The address transition detection signal is composed of a one shot pulse.By using a start-point edge of the one shot pulse as a trigger togenerate a testing refresh pulse signal a preset second predeterminedtime after the trigger, it is possible to carry out tests under a secondtiming condition that the read or write operation is started a secondtime interval after the refresh operation has been finished. The secondtime interval may be set to the smallest value possible for the circuitconfiguration.

The second predetermined time may be set on the basis of the timebetween a rising edge of the address transition detection signal and arise in a word line for the read or write operation minus the sum of thetime corresponding to a word pulse width for the self-refresh operationand the second time interval, as well as the delay time between thepreset signals.

A test mode switch signal can be performed to switch between the testsunder the first timing condition and the tests under the second timingcondition during the test operation mode.

The refresh operation in the test operation mode can be performed basedon an address internally generated by the semiconductor memory device.

The refresh operation in the test operation mode can be performed basedon the externally inputted address.

Moreover, the present invention provides a semiconductor memory devicehaving a plurality of memory cells to be refreshed, the devicecomprising access control means for controlling accesses to the memorycells using as a trigger a status transition timing for an externallyinputted signal status change detection signal that detects a change inthe status of an externally inputted signal, refresh address generatingmeans for automatically generating a refresh address, first refreshtiming control signal generating means for automatically generating afirst refresh timing control signal for determining a refresh timing ina normal operation mode, a second refresh timing control signalgenerating means for using the status transition timing for theexternally inputted signal status change detection signal as a triggerto generate a second refresh timing control signal for determining arefresh timing in a test operation mode a preset predetermined timeafter the trigger, and a refresh timing switching means for selectingand supplying the first refresh timing control signal to the accesscontrol means in the normal operation mode and selecting and supplyingthe second refresh timing control signal to the access control means inthe test operation mode, wherein the timing for the refresh operation inthe test operation mode is set using as a trigger the status transitiontiming for the externally inputted signal status change detection signalso that the time interval between the timings for the refresh operationand for a read or write operation has an externally set value.

The refresh timing switching means may comprise operation mode switchsignal generating means for generating an operation mode switch signalthat switches between the normal operation mode and the test operationmode on the basis of the externally inputted signal, and first switchingmeans for selecting the first refresh timing control signal in thenormal operation mode or selecting the second refresh timing controlsignal in the test operation mode, on the basis of the operation modeswitch signal, and supplying the selected refresh timing signal to theaccess control means.

The externally inputted signal status change detection signal may havean address transition detection circuit that generates an addresstransition detection signal depending on at least one of a timing for achange in an externally inputted address and a status transition timingfor a signal that selectively activates the semiconductor memory device.The signal selectively activating the semiconductor memory device is,for example, a chip select signal.

The second refresh timing control signal generating means may use thestatus transition timing for the address transition detection signal asa trigger to generate a testing refresh pulse signal a preset firstpredetermined time after the trigger, thus carrying out tests under afirst timing condition that the refresh operation is started a firsttime interval after the read or write operation has been finished. Thefirst time interval may be set to the smallest value possible for acircuit configuration.

The second refresh timing control signal generating means may use anend-point edge of the one shot pulse as a trigger to generate the secondrefresh timing control signal the first predetermined time after thetrigger, the first predetermined time corresponding to the timedetermined on the basis of the sum of the time for which a word line canbe kept active and the first time interval as well as the delay timebetween preset signals.

The second refresh timing control signal generating means may use astart-point edge of the one shot pulse as a trigger, and the firstpredetermined time may be set on the basis of the pulse width of theaddress transition detection signal, and the sum of the time for which aword line can be kept active and the first time interval, as well as thedelay time between the preset signals.

The second refresh timing control signal generating means may use as atrigger a start-point edge of the one shot pulse operating as theaddress transition detection signal to generate a testing refresh pulsesignal a preset second predetermined time after the trigger, thuscarrying out tests under a second timing condition that the read orwrite operation is started a second time interval after the refreshoperation has been finished. The second time interval may be set to thesmallest value possible for the circuit configuration.

The second predetermined time may be set on the basis of the timebetween a rising edge of the address transition detection signal and arise in a word line for the read or write operation minus the sum of thetime corresponding to a word pulse width for the self-refresh operationand the second time interval, as well as the delay time between thepreset signals.

A test mode switch signal supplied by the refresh timing switch meansmay be inputted to the second refresh timing control signal generatingmeans, and if the test mode switch signal specifies tests under thefirst timing condition, the second refresh timing control signalgenerating means may use the status transition timing for the addresstransition detection signal as a trigger to generate a first testingrefresh pulse signal a preset first predetermined time after thetrigger, thus carrying out tests under a first timing condition that therefresh operation is started a first time interval after the read orwrite operation has been finished, and if the test mode switch signalspecifies tests under the second timing condition, the second refreshtiming control signal generating means may use as a trigger astart-point edge of the one shot pulse operating as the addresstransition detection signal to generate a second testing refresh pulsesignal a preset second predetermined time after the trigger, thuscarrying out tests under a second timing condition that the read orwrite operation is started a second time interval after the refreshoperation has been finished.

The test mode switch signal can be used to switch between the testsunder the first timing condition and the tests under the second timingcondition during the test operation mode.

The second refresh timing control signal generating means may have afirst testing refresh pulse signal generating circuit that generates thefirst testing refresh pulse signal and a second testing refresh pulsesignal generating circuit that generates the second testing refreshpulse signal. In the test mode, the refresh timing switching means mayselect either the first testing refresh pulse signal or the secondtesting refresh pulse signal on the basis of the test mode switch signaland supply the selected testing refresh pulse signal to the accesscontrol means.

The first testing refresh pulse generating circuit may use as a triggeran end-point edge of the address transition detection signal composed ofa one shot pulse to generate the first testing refresh pulse signal thefirst predetermined time after the trigger, the first predetermined timecorresponding to the time determined on the basis of the sum of the timefor which a word line can be kept active and the first time interval, aswell as the delay time between the preset signals.

The first testing refresh pulse generating circuit may use as a triggera start-point edge of the address transition detection signal composedof a one shot pulse to generate the first testing refresh pulse signalthe first predetermined time after the trigger, the first predeterminedtime corresponding to the time determined on the basis of the pulsewidth of the address transition detection signal, and the sum of thetime for which a word line can be kept active and the first timeinterval, as well as the delay time between the preset signals.

The second testing refresh pulse generating circuit may use as a triggera start-point edge of the one shot pulse operating as the addresstransition detection signal to generate the second testing refresh pulsesignal the second predetermined time after the trigger, the secondpredetermined time corresponding to the time determined on the basis ofthe time between a rising edge of the address transition detectionsignal and a rise in a word line for the read or write operation minusthe sum of the time corresponding to a word pulse width for theself-refresh operation and the second time interval, as well as thedelay time between the preset signals.

The semiconductor memory device may further comprise externally inputtedaddress retaining means for retaining an externally inputted address,and refresh address switching means for selecting, in the normaloperation mode, a first refresh address supplied by the refresh addressgenerating means or selecting, in the test operation mode, a secondrefresh address supplied by the externally inputted address retainingmeans.

Moreover, the present invention provides a test circuit comprising asemiconductor memory device having a plurality of memory cells to berefreshed, the device comprising testing refresh timing control signalgenerating means for using as a trigger an externally inputted signalstatus change detection signal that detects a change in the status of anexternally inputted signal, to generate a testing refresh timing controlsignal a preset predetermined time after the trigger, the testingrefresh timing control signal being used to determine a refresh timingin a test operation mode, and refresh timing switching means forselecting and supplying a normal operation refresh timing control signalto access control means of the semiconductor memory device in a normaloperation mode and selecting and supplying the testing refresh timingcontrol signal to the access control means in a test operation mode,wherein the timing for the refresh operation in the test operation modeis set using the externally inputted signal status change detectionsignal as a trigger so that the time interval between the timings forthe refresh operation and for a read or write operation has anexternally set value.

The refresh timing switching means may comprise an operation mode switchsignal generating means for generating an operation mode switch signalin order to switch between the normal operation mode and the testoperation mode on the basis of the externally inputted signal, and firstswitching means for selecting the first refresh timing control signal inthe normal operation mode or selecting the second refresh timing controlsignal in the test operation mode and supplying the selected refreshtiming control signal to the access control means.

The externally inputted signal status change detection signal maycomprise an address transition detection signal generated depending onat least one of a timing for a change in an externally inputted addressand a status transition timing for a signal that selectively activatesthe semiconductor memory device. The signal selectively activating thesemiconductor memory device is, for example, a chip select signal.

The testing refresh timing control signal generating means may use thestatus transition timing for the address transition detection signal asa trigger to generate a testing refresh pulse signal a preset firstpredetermined time after the trigger, thus carrying out tests under afirst timing condition that the refresh operation is started a firsttime interval after the read or write operation has been finished. Thefirst time interval may be set to the smallest value possible for acircuit configuration.

The testing refresh timing control signal generating means may use as atrigger an end-point edge of the address transition detection signalcomposed of one shot pulse to generate the second refresh timing controlsignal the first predetermined time after the trigger, the firstpredetermined time corresponding to the time determined on the basis ofthe sum of the time for which a word line can be kept active and thefirst time interval as well as the delay time between preset signals.

The testing refresh timing control signal generating means may use as atrigger an start-point edge of the address transition detection signalcomposed of one shot pulse and the first predetermined time may be seton the basis of the pulse width of the address transition detectionsignal, and the sum of the time for which a word line can be kept activeand the first time interval, as well as the delay time between thepreset signals.

The testing refresh timing control signal generating means may use as atrigger a start-point edge of the one shot pulse operating as theaddress transition detection signal to generate a testing refresh pulsesignal a preset second predetermined time after the trigger, thuscarrying out tests under a second timing condition that the read orwrite operation is started a second time interval after the refreshoperation has been finished. The second time interval may be set to thesmallest value possible for the circuit configuration.

The second predetermined time may be set on the basis of the timebetween a rising edge of the address transition detection signal and arise in a word line for the read or write operation minus the sum of thetime corresponding to a word pulse width for the self-refresh operationand the second time interval, as well as the preset delay time betweenthe preset signals.

A test mode switch signal supplied by the refresh timing switch meansmay be inputted to the testing refresh timing control signal generatingmeans, and if the test mode switch signal specifies tests under thefirst timing condition, the testing refresh timing control signalgenerating means may use the status transition timing for the addresstransition detection signal as a trigger to generate a first testingrefresh pulse signal a preset first predetermined time after thetrigger, thus carrying out tests under a first timing condition that therefresh operation is started a first time interval after the read orwrite operation has been finished.

If the test mode switch signal specifies tests under the second timingcondition, the testing refresh timing control signal generating meansmay use as a trigger a start-point edge of the one shot pulse operatingas the address transition detection signal to generate a second testingrefresh pulse signal a preset second predetermined time after thetrigger, thus carrying out tests under a second timing condition thatthe read or write operation is started a second time interval after therefresh operation has been finished.

The test mode switch signal can be used to switch between the testsunder the first timing condition and the tests under the second timingcondition during the test operation mode.

The testing timing control signal generating means may have a firsttesting refresh pulse signal generating circuit that generates the firsttesting refresh pulse signal and a second testing refresh pulse signalgenerating circuit that generates the second testing refresh pulsesignal. In the test mode, the refresh timing switching means may selecteither the first testing refresh pulse signal or the second testingrefresh pulse signal on the basis of the test mode switch signal andsupply the selected testing refresh pulse signal to the access controlmeans.

The first testing refresh pulse generating circuit may use as a triggeran end-point edge of the address transition detection signal composed ofa one shot pulse to generate the first testing refresh pulse signal thefirst predetermined time after the trigger, the first predetermined timecorresponding to the time determined on the basis of the sum of the timefor which a word line can be kept active and the first time interval, aswell as the delay time between the preset signals.

The first testing refresh pulse generating circuit may use as a triggera start-point edge of the address transition detection signal composedof a one shot pulse to generate the first testing refresh pulse signalthe first predetermined time after the trigger, the first predeterminedtime corresponding to the time determined on the basis of the pulsewidth of the address transition detection signal, and the sum of thetime for which a word line can be kept active and the first timeinterval, as well as the preset delay time between the preset signals.

The second testing refresh pulse generating circuit may use as a triggera start-point edge of the one shot pulse operating as the addresstransition detection signal to generate the second testing refresh pulsesignal the second predetermined time after the trigger, the secondpredetermined time corresponding to the time determined on the basis ofthe time between a rising edge of the address transition detectionsignal and a rise in a word line for the read or write operation minusthe sum of the time corresponding to a word pulse width for theself-refresh operation and the second time interval, as well as thepreset delay time between the preset signals.

The test circuit may further comprise externally inputted addressretaining means for retaining an externally inputted address, andrefresh address switching means for selecting, in the normal operationmode, a first refresh address supplied by the refresh address generatingmeans or selecting, in the test operation mode, a second refresh addresssupplied by the externally inputted address retaining means.

The test circuit may be built into the semiconductor memory device.Alternatively, the test circuit and the semiconductor memory device maybe mounted on the same chip separately from each other.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing the circuit configuration of asemiconductor memory device (pseudo SRAM) according to a firstembodiment of the present invention;

FIG. 2 is a timing chart showing a normal operation performed by thesemiconductor memory device shown in FIG. 1;

FIG. 3 is a timing chart showing a test operation performed by thesemiconductor memory device shown in FIG. 1;

FIG. 4 is a flow chart showing a test procedure executed by thesemiconductor memory device shown in FIG. 1;

FIG. 5 is a timing chart showing an operation performed in a test modeby a semiconductor memory device according to a second embodiment of thepresent invention;

FIG. 6 is a block diagram showing the circuit configuration of asemiconductor memory device (pseudo SRAM) according to a thirdembodiment of the present invention;

FIG. 7 is a timing chart showing an operation performed in the test modeby the semiconductor memory device shown in FIG. 6;

FIG. 8 is a flow chart showing a test procedure executed by thesemiconductor memory device shown in FIG. 6;

FIG. 9 is a block diagram showing the circuit configuration of asemiconductor memory device (pseudo SRAM) according to a fourthembodiment of the present invention;

FIG. 10 is a timing chart showing an operation performed in the testmode by the semiconductor memory device shown in FIG. 9;

FIG. 11 is a timing chart showing the operation performed in the testmode by the semiconductor memory device shown in FIG. 9;

FIG. 12 is a flow chart showing a test procedure executed by thesemiconductor memory device shown in FIG. 9;

FIG. 13 is a block diagram showing the circuit configuration of asemiconductor memory device (pseudo SRAM) according to a fifthembodiment of the present invention;

FIG. 14 is a timing chart showing an operation performed in the testmode by the semiconductor memory device shown in FIG. 13; and

FIG. 15 is a timing chart showing the operation performed in the testmode by the semiconductor memory device shown in FIG. 13.

BEST MODE FOR CARRYING OUT THE INVENTION First Embodiment

A first embodiment of the present invention will be described below withreference to the drawings.

FIG. 1 is a block diagram showing the circuit configuration of asemiconductor memory device (pseudo SRAM) according to the firstembodiment. FIG. 2 is a timing chart showing a normal operationperformed by the semiconductor memory device shown in FIG. 1. First, thecircuit configuration of the semiconductor memory device (pseudo SRAM)will be described with reference to FIG. 1. With reference to FIG. 2,description will be given of the normal operation performed by thesemiconductor memory device according to the present application.

A read/write address signal Add is externally inputted to an addressbuffer circuit 21. An address transition detecting circuit (ATD circuit)25 is connected to the address buffer circuit 21 to receive theread/write address signal Add as an input. When at least one bit in theaddress data Add changes, the address transition detecting circuit 25detects the change to output an address transition detection signal ATD.

A row control circuit 26 is connected to an output of the addresstransition detecting circuit (ATD circuit) 25 to generate and output arow enable signal RE, a sense enable signal SE, and a column controlsignal CC on the basis of the address transition detection signal ATD,outputted by the address transition detecting circuit (ATD circuit) 25.Here, the row enable signal RE is a pulse signal that rises in responseto a fall in the address transition detection signal ATD and that fallsa specified time later, as shown in FIG. 2. The sense enable signal SEis obtained by delaying the row enable signal RE a specified time.Although not shown, the column control signal CC is obtained by delayinga pulse signal a specified time, the pulse signal being based on a fallin the address transition detection signal ATD.

The column control circuit 27 is connected to a row control circuit 26to receive the column control signal CC outputted by the row controlcircuit 26. The column control circuit 27 further delays the columncontrol signal CC and outputs the delayed signal as the column enablesignal CE.

A memory cell array 30 has a configuration similar to that of a memorycell array in a DRAM. A row decode circuit 31 connected to word lines inthe memory cell array 30 is also connected to the row control circuit26. When a row enable signal RE outputted by the row control circuit 26changes to H, the row decode circuit 31 selectively activates a wordline in the memory cell array 30 corresponding to row address data MAddoutputted by a second switching circuit (MUX2) 42.

A sense amplifier circuit 33 connected to each bit line in the memoryarray circuit 30 is also connected to the row control circuit 26. When asense enable signal SE outputted by the row control circuit 26 changesto H, the sense amplifier circuit 33 activates each bit line in thememory cell array 30.

A column decode circuit 35 is connected to the previously describedaddress buffer circuit 21 and column control circuit 27. When the columnenable signal CE outputted by the column control circuit 27 changes toH, the column decode circuit 35 decode column address data Addccontained in the address data Add. The column decode circuit 35 thenconnects a sense amplifier corresponding to the result of the decode, toan input/output data terminal 37 via an I/O buffer 36.

A timer circuit 50 outputs timing signals TM at fixed time intervals andsupplies the signals TM to a refresh pulse generating circuit 60.

The refresh pulse generating circuit 60 generates refresh timings for anormal operation. The refresh pulse generating circuit 60 is connectedto an output of the timer circuit 50 to receive the timing signal TM asan input. An output of the refresh pulse generating circuit 60 isconnected to the first switching circuit (MUX1) 41. Specifically, therefresh pulse generating circuit 60 supplies a normal refreshing pulsesignal REF to the first switching circuit (MUX1) 41 on the basis of thetiming signals TM, outputted at the fixed time intervals.

A first testing refresh pulse generating circuit 62 generates testingrefresh timings for operation check tests. The first testing refreshpulse generating circuit 62 is connected to an output of the addresstransition detecting circuit (ATD circuit) 25. The first testing refreshpulse generating circuit 62 receives the address transition detectionsignal ATD as an input to generate a first testing refresh pulse signalTREF1. An output of the first testing refresh pulse generating circuit62 is connected to the first switching circuit (MUX1) 41. Specifically,on the basis of the address transition detection signal ATD, the firsttesting refresh pulse generating circuit 62 supplies the first testingrefresh pulse signal TREF1 to the first switching circuit (MUX1) 41.

A test mode entry circuit 53 externally controls the switching between anormal operation mode and a test mode. The test mode entry circuit 53receives a test mode entry signal TE as an input and outputs andsupplies a first operation mode switch signal TE1 to the first switchingcircuit (MUX1) 41.

The first switching circuit (MUX1) 41 switches a refresh timingdepending on the operation mode (normal operation mode or test mode). Aninput of the first switching circuit (MUX1) 41 is connected to an outputof the test mode entry circuit 53, an output of the refresh pulsegenerating circuit 60, and an output of the first testing refresh pulsegenerating circuit 62. The first switching circuit (MUX1) 41 receivesthe first operation mode switch signal TE1, the normal refreshing pulsesignal REF, and the first testing refresh pulse signal TREF1 as inputsto generate a refresh timing control signal RF.

An output of the first switching circuit (MUX1) 41 is connected to therow control circuit 26, the refresh address generating circuit 66, andthe second switching circuit (MUX2) 42. The first switching circuit(MUX1) 41 supplies the refresh timing control signal RF to the rowcontrol circuit 26, the refresh address generating circuit 66, and thesecond switching circuit (MUX2) 42. That is, in response to the firstoperation mode switch signal TE1, the first switching circuit (MUX1) 41outputs as RF either a timing control signal based on the normalrefreshing pulse signal REF or a timing control signal based on thefirst testing refresh pulse signal TREF1.

The refresh address generating circuit 66 is connected to the output ofthe first switching circuit (MUX1) 41 to receive the refresh timingcontrol signal RF as an input. The output of the refresh addressgenerating circuit 66 is connected to the second switching circuit(MUX2) 42 to supply it with a refresh address RAdd. The refresh addressgenerating circuit 66 uses the refresh timing control signal RF as atrigger to count up the refresh address. The refresh address generatingcircuit 66 then supplies the refresh address to the second switchingcircuit (MUX2) 42.

The second switching circuit (MUX2) 42 is connected to the outputs ofthe address buffer circuit 21, refresh address generating circuit 66,and first switching circuit (MUX1) 41. The second switching circuit(MUX2) 42 receives the row address data AddR, the refresh address RAdd,and the refresh timing control signal RF as inputs to generate a rowaddress MAdd that specifies a memory cell to be accessed. An output ofthe second switching circuit (MUX2) 42 is connected to the row decodecircuit 31 to supply it with the row address MAdd. Specifically, when aself refresh operation is determined to have been activated on the basisof the logical level (0 or 1) of the refresh timing control signal RF,that is, when the logical level of the refresh timing control signal RFchanges from L to H, the second switching circuit (MUX2) 42 outputs therefresh address RAdd. Otherwise, the second switching circuit (MUX2) 42outputs the row address data AddR.

The test mode entry circuit 53 externally controls the switching betweenthe normal operation mode and the test mode. The test mode entry circuit53 receives the test mode entry signal TE as an input and outputs andsupplies the first operation mode switch signal TE1 to the firstswitching circuit (MUX1) 41.

Now, separate description will be given of a test mode operation and anormal operation performed by the above described semiconductor memorydevice.

First, the normal operation will be described with reference to FIG. 2.In this case, the test mode entry signal TE is set to L to set the firstoperation mode switch signal TE1, outputted by the test mode entrycircuit 53, to L. When TE=0, that is, during the normal operation, thetest circuit does not operate. Accordingly, the operation of thesemiconductor memory device is substantially the same as that of asemiconductor memory device not having a built-in test circuit.

First, a read and write operations will be described. At a time T1, theread/write address Add changes from “A0” to “A1”. Then, the addresstransition detecting circuit (ATD circuit) 25 senses the change inaddress. At a time T2, the address transition detecting circuit (ATDcircuit) 25 raises and supplies the address transition detection signalATD to the row control circuit 26 and second switching circuit (MUX2) 42as a positive one shot pulse signal. Here, the addresses A0 and A1 arerow-based addresses. In the description of the example below, only therow-based addresses change.

Further, as the read/write address signal Add changes, the row addressMAdd switches from “A0” to “A1” at a time T3. At this time, the secondswitching circuit (MUX2) 42 supplies the row address data AddR to therow decode circuit 31 as the row address MAdd. This is because thesecond switching circuit (MUX42) determines that the self refreshoperation has not been activated because the refresh timing controlsignal RF, an output signal from the first switching circuit (MUX1) 41is L.

Upon receiving the address transition detection signal ATD, the rowcontrol circuit 26 uses a falling edge of the address transitiondetection signal ATD at a time T4 as a trigger to raise the row enablesignal RE at a time T5. The row control circuit 26 supplies the rowdecode circuit 31 with the row enable signal RE having a predeterminedpulse length. Since the second switching circuit (MUX2) 42 has alreadyinputted the row address MAdd to the row decode circuit 31, the a wordline Word specified by the row address MAdd (AddR=A1) is activatedsynchronously with the row enable signal RE at a time T6.

The row control circuit 26 uses the falling edge of the addresstransition detection signal ATD at the time T4 as a trigger to raise thesense enable signal SE at a time T7. The row control circuit 26 thensupplies the sense enable signal SE to the sense amplifier circuit 33 toactivate it. Moreover, the row control circuit 26 uses the falling edgeof the address transition detection signal ATD at the time T4 as atrigger to raise and supply the column control signal CC to the columncontrol circuit 27. Then, the column control circuit 27 uses a timingbased on the column control signal CC (and thus on the row enable signalRE) to raise and supply the column enable signal CE to the column decodecircuit 35 at a time T8. A column-based address AddC is inputted to thecolumn decode circuit 35.

Upon receiving the column enable signal CE, the column decode circuit 35decodes the column address data AddC and connects a sense amplifier 33corresponding to the result of the decode to the input/output dataterminal 37 via the I/O buffer 36. Thus, for a read operation, datastored in a cell specified by the row address A1 in the memory cellarray 30 is transmitted to the input/output data terminal 37 via thesense amplifier 33 and the I/O buffer 36. For a write operation, datapresent on the input/output data terminal 37 is written in the cellspecified by the row address A1 in the memory cell array 30.

A predetermined time after the falling edge of the address transitiondetection signal ATD at the time T4, each of the row enable signal RE,column enable signal CE, and column enable signal CE falls. The read andwrite operations in the normal mode have been described.

Now, the self refresh operation in the normal mode will be described.The self refresh operation is activated at fixed time intervals on thebasis of internally generated timings and addresses regardless ofexternally inputted signals.

Activation timings for the self refresh operation are generated by thetimer circuit 50. At a time T10, the timer circuit 50 outputs the oneshot pulse signal TM having a predetermined pulse width. Then, uponreceiving the signal TM, on the basis of a rising edge of the signal TM,the refresh pulse generating circuit 60 outputs the normal refreshingpulse signal REF as a one shot pulse signal having a pulse widthcorresponding to the time required for one refresh operation. Therefresh pulse generating circuit 60 supplies the normal refreshing pulsesignal REF to the first switching circuit (MUX1) 41.

On the other hand, the refresh address RAdd is generated by the refreshaddress generating circuit 66. In the description below, at a time T10,when the signal TM is outputted, the refresh address generating circuit66 is assumed to generate “R0” as the refresh address RAdd and supply itto the second switching circuit (MUX2) 42.

For the normal operation, the first switching circuit (MUX1) 41 outputsthe refresh timing control signal RF on the basis of the normalrefreshing pulse signal REF. In response to a rise in the refresh timingcontrol signal RF which occurs a short time delay after the time T10,the second switching circuit (MUX2) 42 determines that the self refreshoperation has been activated. Thus, the row address MAdd is switched toRAdd=R0.

In response to the rise in the refresh timing control signal RF, the rowenable signal RE rises at a time T11. Since the refresh address RAdd hasalready been supplied to the row decode circuit 31, a word line Wordspecified by RAdd=R0 is activated synchronously with the row enablesignal RE at a time T12.

Moreover, at a time T13, the sense enable signal SE rises to activatethe sense amplifier circuit 33. Then, the memory cell connected to theactivated word line Word is refreshed. Thus, the memory cell specifiedby the refresh address RAdd (R0) is completely refreshed.

At a time T14, the refresh timing control signal RF falls. Then, thesecond switching circuit (MUX2) 42 determines that the self refreshoperation has been finished. The second switching circuit (MUX2) 42 thusswitches the row address MAdd from the refresh address RAdd (R0) to therow address data AddR (A1). Further, a fall in the refresh timingcontrol signal RF is inputted to the refresh address generating circuit66. The refresh address generating circuit 66 then uses this signal as atrigger to count up the refresh address RAdd to switch it to R1.

Moreover, at a time T15, the read/write address signal Add changes from(A1) to (A2). In response to this change, at a time T16, the row addressdata MAdd changes from (A1) to (A2). Subsequently, a word line Wordspecified by the row address MAdd (AddR=A2) is activated, and the reador write operation in the normal operation mode is performed.

As described above, the read or write operation is performedindependently of the self refresh operation. Accordingly, measures mustbe taken to prevent the operation timings from overlapping each other.

As a first measure, it is contemplated that operations may be controlledso as to avoid performing two operations at the same time.

As a second measure, it is necessary to ensure that interference-inducedmalfunction is prevented in spite of the short time interval between theoperation timings. That is, operation checks are executed by forcedlyintroducing the shortest time intervals possible for the circuitconfiguration into operations to confirm the avoidance of malfunction.

The present invention takes the second measure. Specifically, thepresent invention executes operation checks on the time intervals “t1”and “t2” in FIG. 2. “t1” is the time interval in which the self refreshoperation is activated immediately after the read or write operation hasbeen completed to release the self refresh operation that has beenprohibited by the first measure. Like “t2”, “t1” is the time interval inwhich the read/write address signal “Add” changes to reduce the timeinterval between the self refresh operation and the read or writeoperation immediately after the internal timer circuit 50 has activatedthe self refresh operation. Values for “t1” and “t2” depend on thecircuit configuration. In the first embodiment shown in FIG. 1, acondition for “t1” is generated by a first testing refresh pulsegenerating circuit 62. In the second embodiment, shown in FIG. 6, acondition for “t2” is generated by a second testing refresh pulsegenerating circuit 64.

Now, with reference to FIG. 1, a brief description will be given of anoperation performed in the test mode by the semiconductor memory deviceaccording to the present embodiment. A detailed description will begiven later with also reference to FIG. 3.

The test mode entry signal TE is activated and TE=H is inputted to thetest mode entry circuit 53. Then, the semiconductor memory devicerecognizes that the test mode has been entered. That is, thesemiconductor memory device is set in the test mode.

In the previously described normal operation mode, operation timings areindependently provided for the read or write operation and for the selfrefresh operation. However, in the test mode, these operation timingsare associated with one another. In the case described below, theself-refresh operation is performed a predetermined time after the reador write operation.

When the test mode entry signal TE becomes 1, the first operation modeswitch signal TE1, outputted by the test mode entry circuit 53, alsobecomes 1. The first switching circuit (MUX1) 41, to which the firstoperation mode switch signal TE1 (TE1=1) is inputted, determines thatthe test mode has been entered. On the basis of the timing signal TMfrom the timer circuit 50, the first switching circuit (MUX1) 41 thendeselects the normal refreshing pulse signal REF, outputted by therefresh pulse generating circuit 60. On the other hand, the firstswitching circuit (MUX1) 41 selects the first refresh pulse signalTREF1, outputted by the first testing refresh pulse generating circuit62, to output it as the refresh timing control signal RF.

The pulse width of the first testing refresh pulse signal TREF1 must beequal to that of the normal refresh pulse signal REF. This is because ifthe operating conditions other than a parameter to be checked varybetween the normal operation mode and the test mode, the effects ofextra parameters must be considered. This may prevent accurate operationchecks.

The first testing refresh pulse signal TREF1 rises a predetermined time(TA1′) after a falling edge of the address transition detection signalATD outputted by the address transition detection circuit (ATD circuit)25 when the circuit 25 detects a change in the externally inputtedread/write address signal Add. Accordingly, the refresh timing controlsignal RF, outputted by the first switching circuit (MUX1) 41, rises apredetermined time (TA1) after a falling edge of the address transitiondetection signal ATD. The predetermined time (TA1′) is equal to thepredetermined time “TA1” shown in FIG. 3 minus the sum of the timecorresponding to the signal delay between the refresh timing controlsignal RF and the first testing refresh pulse signal TREF1.

A rise timing for the first testing refresh pulse signal TREF1, that is,the predetermined time (TA1′) is preset on the basis of the time theself refresh operation is to be delayed with respect to the read orwrite operation. This is the subject of the test mode operationaccording to the present embodiment.

Specifically, the predetermined time (TA1′) is based on the sum of thetime for which the word line is kept active (selected), that is, thepulse width of the word line, and the shortest time interval possiblefor the circuit configuration represented at “t1” in FIG. 3, as well asthe delay time between the signals.

The first testing refresh pulse generating circuit 62 has a function todetect a fall in the address transition detection signal ATD, outputtedby the address transition detection circuit (ATD circuit) 25, and thepredetermined time (TA1′) after the detected fall timing, generate thefirst testing refresh pulse signal TREF1. The first testing refreshpulse generating circuit 62 can be constructed using a known fallingedge detecting circuit and a known circuit that clocks a predeterminedtime.

The first testing refresh pulse generating circuit 62 may be configuredto detect a rise in the address transition detection signal ATD,outputted by the address transition detecting circuit (ATD circuit) 25and generate the first testing refresh pulse signal TREF1 the total timeof the predetermined time (TA1′) and the pulse width of the addresstransition detection signal ATD after the detected rise timing. In thiscase, the first testing refresh pulse generating circuit 62 can beconstructed using a known rising edge detecting circuit and a knowncircuit that clocks a predetermined time.

Subsequently, the test mode operation will be described with referenceto the timing chart in FIG. 3. At a time T31, the read/write addresssignal Add changes from “A0” to “A1”. Then, the address transitiondetecting circuit (ATD circuit) 25 senses the change in address. At atime T32, the address transition detecting circuit (ATD circuit) 25raises and supplies the address transition detection signal ATD to therow control circuit 26 as a positive one shot pulse signal.

Further, as the right/write address signal Add changes, the row addressMAdd switches from “A0” to “A1” at a time T33. At this time, the secondswitching circuit (MUX2) 42 supplies the row address data AddR to therow decode circuit 31 as the row address MAdd. This is because thesecond switching circuit (MUX2) 42 determines that the self refreshoperation has not been activated because the refresh timing controlsignal RF, an output signal from the first switching circuit (MUX1) 41is L.

Upon receiving the address transition detection signal ATD, the rowcontrol circuit 26 uses a falling edge of the address transitiondetection signal ATD at a time T34 as a trigger to raise the row enablesignal RE at a time T35. The row control circuit 26 supplies the rowdecode circuit 31 with the row enable signal RE having a predeterminedpulse length. Since the second switching circuit (MUX2) 42 has alreadyinputted the row address MAdd to the row decode circuit 31, the a wordline Word specified by the row address MAdd (AddR=A1) is activatedsynchronously with the row enable signal RE at a time T36.

The row control circuit 26 uses the falling edge of the addresstransition detection signal ATD at the time T34 as a trigger to raisethe sense enable signal SE at a time T37. The row control circuit 26then supplies the sense enable signal SE to the sense amplifier circuit33 to activate it. Moreover, the row control circuit 26 uses the fallingedge of the address transition detection signal ATD at the time T34 as atrigger to raise and supply the column control signal CC to the columncontrol circuit 27. Then, the column control circuit 27 uses a timingbased on the column control signal CC (and thus based on the row enablesignal RE) to raise and supply the column enable signal CE to the columndecode circuit 35 at a time T38. A column-based address AddC is inputtedto the column decode circuit 35.

Upon receiving the column enable signal CE, the column decode circuit 35decodes the column address data AddC and connects the sense amplifier 33corresponding to the result of the decode to the input/output dataterminal 37 via the I/O buffer 36. Thus, for a read operation, datastored in a cell specified by the row address A1 in the memory cellarray 30 is transmitted to the input/output data terminal 37 via thesense amplifier 33 and the I/O buffer 36. For a write operation, datapresent on the input/output data terminal 37 is written in the cellspecified by the row address A1 in the memory cell array 30.

A predetermined time after the falling edge of the address transitiondetection signal ATD at the time T34, each of the row enable signal RE,column enable signal CE, and column enable signal CE falls. The read andwrite operations in the test mode have been described.

Now, the self refresh operation in the test mode will be described. Theself refresh operation is activated in association with an externallyinputted signal on the basis of internally generated timings andaddresses.

The first testing refresh pulse generating circuit 62 detects a fallingedge of the address transition detection signal ATD at the time T34. Thepredetermined time (TA1′) after the time T34, the first testing refreshpulse generating circuit 62 generates the first testing refresh pulsesignal TREF1 as a one shot pulse signal having a pulse widthcorresponding to the time required for one refresh operation. Aspreviously described, the pulse width of the first testing refresh pulsesignal TREF1 is set to be the same as that of the normal refreshingpulse signal REF.

Accordingly, the first testing refresh pulse signal TREF1 is supplied tothe first switching circuit (MUX1) 41. Thus at a time T40, the firsttesting refresh pulse signal TREF1 is supplied to the second switchingcircuit (MUX2) 42 as the refresh timing control signal RF having thesame pulse width as that of the normal refreshing pulse signal REF.

On the other hand, the refresh address RAdd is generated by the refreshaddress generating circuit 66. In the description below, the refreshaddress generating circuit 66 is assumed to generate “R0” as the refreshaddress RAdd and supply it to the second switching circuit (MUX2) 42.

For the test mode operation, the first switching circuit (MUX1) 41outputs the refresh timing control signal RF on the basis of the firsttesting refresh pulse signal TREF1. In response to a rise in the refreshtiming control signal RF at a time T40, the second switching circuit(MUX2) 42 determines at a time T41 that the self refresh operation hasbeen activated. Thus, the row address MAdd is switched to RAdd=R0.

Furthermore, in response to the rise in the refresh timing controlsignal RF at the time T40, the second switching circuit (MUX2) 42 raisesthe row enable signal RE and supplies the row decode circuit 31 with therow enable signal having a predetermined pulse width at a time T42.Since the second switching circuit (MUX2) 42 has already inputted therefresh address RAdd to the row decode circuit 31, the word line Wordspecified by the row address MAdd (AddR=R0) is activated synchronouslywith the row enable signal RE at a time T43.

The row control circuit 26 uses the rising edge of the refresh timingcontrol signal RF at the time T40 as a trigger to raise and supply thesense enable signal SE to the sense amplifier circuit 33 to activate itat a time T44. Thus, the memory cell specified by the refresh addressRAdd (R0) is refreshed.

Subsequently at a time T45, the refresh timing control signal RF falls.Then, the second switching circuit (MUX2) 42 determines that the selfrefresh operation has been finished. The second switching circuit (MUX2)42 thus switches the row address MAdd from the refresh address RAdd (R0)to the row address data AddR (A1). Further, a fall in the refresh timingcontrol signal RF is inputted to the refresh address generating circuit66. The refresh address generating circuit 66 then uses this signal as atrigger to count up the refresh address RAdd to switch it to R1.

The predetermined time (TA1) is based on the total time of the pulsewidth of a specified word line, corresponding to the time between thetime T36 and the time T39, and the time interval “t1”, corresponding tothe time between the time T39 and the time T43, as well as the delaytime between the signals. The delay time depends on the individualcircuit configurations but can be pre-calculated on the basis of thecircuit configuration. Accordingly, the predetermined time (TA1) can beset so that the time interval “t1”, corresponding to the time betweenthe time T39 and the time T43, has the smallest value possible for thecircuit configuration.

Therefore, it is possible to carry out tests by forcedly generating acondition that the time interval between the read or write operation andthe self refresh operation has the smallest value “t1” possible for thecircuit configuration.

Subsequently, with reference to the flow chart in FIG. 4, descriptionwill be given of a procedure of testing the semiconductor device.

First, if any chip has a fixed defect or any memory cell has aninadequate hold characteristic, it is meaningless to carry out tests onthe refresh operation. Accordingly, hold tests are pre-executed (stepS1). The hold tests may follow a known test procedure similar to thatfor tests carried out on general-purpose DRAMs.

Specifically, it is assumed that after data has been written in a memorycell in the memory cell array 30 and the refresh has been keptprohibited for a predetermined time, the data is read from this memorycell. In this case, the hold time for this memory cell is determined byadjusting the above predetermined time (that is, refresh cycle) so thatthe read data equals the written data. This test is carried out on allthe memory cells to determine a value for a refresh cycle correspondingto a memory cell with the shortest hold time.

Then, to determine after the tests whether or not the refresh operationand read/write operation have been correctly performed on the memorycell, a test pattern is written in the memory cell array 30 (step S2).

Then, an arbitrary hold time is set (step S3). TE=1 is then inputted toraise the first operation mode switch signal TE1 to H to set the circuitin the test mode (step S4).

Then, an arbitrary read/write address signal Add is applied to theaddress terminal (step S5). The refresh address RAdd, generated by theinternally provided refresh address generating circuit 66, is used.

The above process allows the sequential performance of a read or writeoperation with the row address “A1” shown in FIG. 3 and the self refreshoperation with the row address “R0”, which is performed the shortesttime interval “t1” after the read or write operation.

Then, the data is read from the memory cell connected to the word linespecified by the above address and a data check is executed (step S6).If the result of the check is “NG”, the test is ended and the chip isdiscarded (step S8). If the result of the check is “PASS”, it isdetermined whether or not all the tests have been finished (step S7). Ifthe result of the determination is “NO”, the procedure returns to thestep S5.

Subsequently, the steps S5 to S7 are repeated until the result of thedetermination of whether or not all the tests have been finished is“YES”. Then, when it is determined that tests have been finished on allpatterns to be checked, TE is set to 0, thereby exiting from test modeto finish the tests.

In actuality, a considerably long time is required to test all possiblepatterns. It is thus possible to introduce regularity into the tests.Specifically, all the patterns are initially checked, and once a certaintendency is found out, any of the patterns are omitted. Techniques totest ordinary memories including DRAMs involve patterns in which defectsare easy to find. It is thus possible to combine test techniques such asMarching and Gallop together. However, of course, all the patterns aredesirably tested.

The first embodiment of the present invention has been described. Sincethe read or write operation of the semiconductor memory device isperformed independently of self refresh operation, it is necessary toensure that interference-induced malfunction is prevented in spite ofthe short time interval between the operation timings for the read orwrite operation and for the self refresh operation. The first embodimentraises the first testing refresh pulse signal TREF1 the predeterminedtime (TA1′) after the address transition detection signal ATD haschanged, to set the timing of the self refresh operation to be startedso that time interval between this self refresh operation and thepreceding read or write operation is shortest (t1). This makes itpossible to execute operation checks by forcedly introducing the shortedtime interval possible for the circuit configuration into the operationsto confirm the avoidance of malfunction.

Second Embodiment

A second embodiment of the present invention will be described belowwith reference to the drawings.

The circuit configuration of a semiconductor memory device according tothe present embodiment is the same as that of the semiconductor memorydevice according to the first embodiment. Moreover, the normal modeoperation of the semiconductor memory device according to the presentembodiment is the same as that of the semiconductor memory deviceaccording to the first embodiment. The semiconductor memory deviceaccording to the present embodiment differs from the semiconductormemory device according to the first embodiment only in the test modeoperation. Accordingly, the description of the circuit configuration andnormal mode operation of the semiconductor memory device according tothe present embodiment is omitted. The test mode operation will bedescribed below with reference to FIG. 5. FIG. 5 is a timing chartshowing an operation performed in the test mode by the semiconductormemory device according to the present embodiment.

The testing refresh pulse signal is referred to as the “first testingrefresh pulse signal TREF1” in the first embodiment but as a “secondtesting refresh pulse signal TREF2” in the present embodiment.

The first embodiment sets the timing for starting the self refreshoperation so as to minimize the time interval between the self refreshoperation and the preceding read or write operation, by raising thefirst testing refresh pulse signal TREF1 the predetermined time (TA1′)after a change in the address transition detection signal ATD. Incontrast, the present embodiment sets the timing so as to minimize thetime interval between the self refresh operation and the succeeding reador write operation, by raising the second testing refresh pulse signalTREF2 the predetermined time (TA2′) after a rise in the addresstransition detection signal ATD. The predetermined time (TA2′)corresponds to the predetermined time “TA2”, shown in FIG. 5, minus thesignal delay between the refresh timing control signal RF and thetesting refresh pulse signal TREF2.

A rise timing for the second testing refresh pulse signal TREF2, thatis, the predetermined time (TA2′), is preset on the basis of the delayin the read or write operation with respect to the refresh operation.This is the subject of the test mode operation according to the presentembodiment.

Specifically, the time from a rise in the address transition detectionsignal ATD to a rise in a word line for a read or write operation isbased on the sum of the predetermined time (TA2′) and the shortest timeinterval possible for the circuit configuration, which intervalcorresponds to the word pulse width in the self refresh operation and“t2” in FIG. 5, as well as the delay time between the signals. That is,the predetermined time (TA2′) is set on the basis of these conditions.

The first testing refresh pulse generating circuit 62 has a function todetect a rise in the address transition detection signal ATD, outputtedby the address transition detection circuit (ATD circuit) 25, and thepredetermined time (TA2′) after the detected rise timing, generate thesecond testing refresh pulse signal TREF2. The first testing refreshpulse generating circuit 62 can be constructed using a known rising edgedetecting circuit and a known circuit that clocks a predetermined time.

The test mode operation will be described below with reference to FIG.5. At a time T51, the read/write address signal Add changes from “A0” to“A1”. Then, the address transition detecting circuit (ATD circuit) 25senses the change in address. At a time T52, the address transitiondetecting circuit (ATD circuit) 25 raises and supplies the addresstransition detection signal ATD to the row control circuit 26 as apositive one shot pulse signal.

Further, as the read/write address signal Add changes, the row addressMAdd switches from “A0” to “A1”. At this time, the second switchingcircuit (MUX2) 42 supplies the row address data AddR to the row decodecircuit 31 as the row address MAdd. This is because the second switchingcircuit (MUX42) determines that the self refresh operation has not beenactivated because the refresh timing control signal RF, an output signalfrom the first switching circuit (MUX1) 41 is L.

Further, the first testing refresh pulse generating circuit 62 detectsthe rising edge of the address transition detection ATD signal at thetime T52. The predetermined time (TA2′) after the time T52, the secondtesting refresh pulse signal TREF2 is generated as a one shot pulsesignal having a pulse width corresponding to the time required for onerefresh operation. The pulse width of the second testing refresh pulsesignal TREF2 is set equal to that of the normal refresh pulse signalREF.

The second testing refresh pulse signal TREF2 is supplied to the firstswitching circuit (MUX1) 41. Then at a time T53, the second testingrefresh pulse signal TREF2 is supplied to the second switching circuit(MUX2) 42 as the refresh timing control signal RF having the same pulsewidth as that of the normal refresh pulse signal REF.

In response to a rise in the refresh timing control signal RF at thetime T53, the second switching circuit (MUX2) 42 determines that theself refresh operation has been activated. Thus, the row address MAdd isswitched to RAdd=R0.

Furthermore, in response to the rise in the refresh timing controlsignal RF at the time T53, the second switching circuit (MUX2) 42 raisesthe row enable signal RE and supplies the row decode circuit 31 with therow enable signal RE having a predetermined pulse width at a time T54.Since the second switching circuit (MUX2) 42 has already inputted therow address MAdd to the row decode circuit 31, the word line Wordspecified by the row address MAdd (AddR=R0) is activated synchronouslywith the row enable signal RE at a time T55.

In response to the rising edge of the refresh timing control signal RFat the time T53, the row control circuit 26 raises and supplies thesense enable signal SE to the sense amplifier circuit 33 to activate itat a time T56. Thus, the memory cell specified by the refresh addressRAdd (R0) is refreshed.

Subsequently at a time T57, the refresh timing control signal RF falls.Then, the second switching circuit (MUX2) 42 determines that the selfrefresh operation has been finished. The second switching circuit (MUX2)42 thus switches the row address MAdd from the refresh address RAdd (R0)to the row address data AddR (A1). Further, a fall in the refresh timingcontrol signal RF is inputted to the refresh address generating circuit66. The refresh address generating circuit 66 then uses this signal as atrigger to count up the refresh address RAdd to switch it to R1.

A predetermined time (T58) later, the row enable signal RE falls tofinish the refresh operation on the memory cell specified by the refreshaddress RAdd (R0).

Subsequently, a falling edge in the address transition detection signalATD at a time T59 is used as a trigger to raise the row enable signal REat T60 and supply the row decode circuit 31 with the row enable signalhaving a predetermined pulse width. Since the second switching circuit(MUX2) 42 has already inputted the row address MAdd to the row decodecircuit 31, the word line Word specified by the row address MAdd(AddR=A1) is activated synchronously with the row enable signal RE at atime T61. Then, the read or write operation is performed as in the caseof Embodiment 1.

The time from the rise in the address transition detection signal ATD atthe time T52 to the rise of the word line for the read or writeoperation at the time T61 is based on the sum of the predetermined time(TA2), the word pulse width in the self refresh operation, correspondingto the time between the time T55 and the time T58, and the shortest timeinterval possible for the circuit configuration, denoted by “t2”, aswell as the delay time between the signals. The delay time depends onthe individual circuit configurations but can be pre-calculated on thebasis of the circuit configuration. Accordingly, the predetermined time(TA2) can be set so that the time interval “t2”, corresponding to thetime between the time T58 and the time T61, has the smallest valuepossible for the circuit configuration.

Therefore, it is possible to carry out tests by forcedly generating acondition that the time interval between the self refresh operation andthe read or write operation has the smallest value “t2” possible for thecircuit configuration.

The procedure of testing the semiconductor memory device is the same asthat in the first embodiment. Accordingly, its description is omitted.

The second embodiment according to the present invention has beendescribed. Since the read or write operation of the semiconductor memorydevice is performed independently of its refresh operation, it isnecessary to ensure that interference-induced malfunction is preventedin spite of the short time interval between the operation timings forthe read or write operation and for the self refresh operation. Thesecond embodiment raises the second testing refresh pulse signal TREF2the predetermined time (TA2′) after the address transition detectionsignal ATD has changed, to set the self refresh operation to be startedso that time interval between this self refresh operation and thepreceding read or write operation is shortest (t2). This makes itpossible to execute operation checks by forcedly introducing the shortedtime interval possible for the circuit configuration into the operationsto confirm the avoidance of malfunction.

Third Embodiment

A third embodiment of the present invention will be described below withreference to the drawings.

The first embodiment generates the first testing refresh pulse signalTREF1 the predetermined time (TA1′) after the address transitiondetection signal ATD has changed, to set the self refresh operation tobe started so that time interval “t1” between this self refreshoperation and the preceding read or write operation is shortest. Thefirst embodiment thus carries out tests under the worst timing condition(hereinafter referred to as the “first worst timing condition”). Thesecond embodiment generates the second testing refresh pulse signalTREF2 the predetermined time (TA2′) after a rise of the addresstransition detection signal ATD, to set the self refresh operation sothat time interval “t2” between this self refresh operation and thepreceding read or write operation is shortest. The second embodimentthus carries out tests under the worst timing condition (hereinafterreferred to as the “second worst timing condition”).

According to the present embodiment, the circuit configurations of thesemiconductor memory devices according to the first and secondembodiments are partly changed so that a semiconductor memory device canperform a testing operation under either the first and second worsttiming condition. The changed parts of the circuit configurations willbe described below with reference to FIG. 6. FIG. 6 is a block diagramshowing the configuration of a semiconductor memory device according tothe third embodiment.

Specifically, this circuit is composed of a first and second testingrefresh pulse generating circuits 62 and 64 to which the addresstransition detection signal ATD from the address transition detectingcircuit (ATD circuit) 25 is inputted, and a third switching circuit(MUX3) 43 which receives a test mode selection signal TS as an input toselect one of the first and second testing refresh pulse signals TREF1and TREF2, outputted by the first and second testing refresh pulsegenerating circuits 62 and 64, respectively, on the basis of a secondoperation mode switch signal TE2 outputted by the test mode entrycircuit 53, and to supply the selected testing refresh pulse signal tothe first switching circuit (MUX1) 41. The test mode entry circuit 53receives the test mode entry signal TE as an input to output the firstoperation mode switch signal TE1. The test mode entry circuit 53 alsoreceives the test mode entry signal TE as an input to output the firsttest mode switch signal TE1. The test mode entry circuit 53 furtherreceives the test mode selection signal TS as an input to output thesecond test mode switch signal TE2 and supplies the first operation modeswitch signal TE1 to the first switching circuit (MUX1) 41 and thesecond test mode switch signal TE2 to the third switching circuit (MUX3)43.

In the present embodiment, in the test mode, which is set by TE=H, thefirst testing refresh pulse signal TREF1 is selected when TS=L. WhenTS=H, the second testing refresh pulse signal TREF2 is selected.Further, when TE=L, the normal operation mode is entered regardless ofthe test mode selection signal TS. The normal operation is the same asthat in the first and second embodiments.

The above time interval “t1” is already set in the first testing refreshpulse generating circuit 62. The first testing refresh pulse generatingcircuit 62 uses a falling edge of the address transition detectionsignal ATD, outputted by the address transition detecting circuit (ATDcircuit) 25, as a trigger. The predetermined time (TA1′) after thefalling edge, the first testing refresh pulse generating circuit 62supplies the first testing refresh pulse signal TREF1 to the thirdswitching circuit (MUX3) 43.

The above time interval “t2” is already set in the second testingrefresh pulse generating circuit 62. The second testing refresh pulsegenerating circuit 62 uses a rising edge of the address transitiondetection signal ATD, outputted by the address transition detectingcircuit (ATD circuit) 25, as a trigger. The predetermined time (TA2′)after the rising edge, the second testing refresh pulse generatingcircuit 62 generates the second testing refresh pulse signal TREF2 andsupplies it to the third switching circuit (MUX3) 43.

As described above, the test mode selection signal TS can be used tocontrol whether to use the first testing refresh pulse signal TREF1 tocarry out tests under the first worst timing condition “t1” or to usethe second testing refresh pulse signal TREF2 to carry out tests underthe second worst timing condition “t2”. For example, the tests may becarried out first under the first worst timing condition and then underthe second worst timing condition. This order may be reversed. If thetests do not require to be carried out under both worst timingconditions, only one of the testing refresh pulse signals may be used asrequired.

The normal mode operation of the semiconductor memory device accordingto the present embodiment is the same as that described in the firstembodiment. If the tests are carried out under the first worst timingcondition “t1” as previously described, the test mode operation is thesame as that described in the first embodiment with reference to FIG. 3except that the third switching circuit (MUX3) 43 selects and suppliesthe first testing refresh pulse signal TREF1, supplied by the firsttesting refresh pulse generating circuit 62, to the first switchingcircuit (MUX2) 41. If the tests are carried out under the second worsttiming condition “t2”, the test mode operation is the same as thatdescribed in the first embodiment with reference to FIG. 5 except thatthe third switching circuit (MUX3) 43 selects and supplies the secondtesting refresh pulse signal TREF2, supplied by the second testingrefresh pulse generating circuit 64, to the first switching circuit(MUX2) 41.

FIG. 7 is a timing chart showing a test operation performed by thesemiconductor memory device according to the present embodiment. FIG. 7shows an example of the relationship between each test operation and thetest mode entry signal TE, test mode selection signal TS, and first andsecond operation mode switch signals TE1 and TE2. As shown in FIG. 7,when TE=1 and TS=0, the tests are carried out under the first worsttiming condition. When TE=1 and TS=1, the tests are carried out underthe second worst timing condition.

Subsequently, with reference to the flow chart in FIG. 8, descriptionwill be given of a procedure of testing the semiconductor memory device.In the description of the example below, the tests are carried out firstunder the first worst timing condition and then under the second worsttiming condition.

First, a hold test (S1) and a memory write (S2) are executed using aprocedure similar to that in Embodiments 1 and 2.

Then, an arbitrary hold time is set (step S3). Next, TE=1 is inputted toraise the first operation mode switch signal TE1 to “H”. The test modeselection signal TS=0 is also inputted to set the second operation modeswitch signal TE2 to L. The third switching circuit (MUX3) 43 is thusset to select the first testing refresh pulse signal TREF1, outputted bythe first testing refresh pulse generating circuit 62 (step S4).

Then, as in the case of Embodiment 1, a read address is set (S5) and thememory is checked (S6). If the result of the check is “NG”, the test isended and the chip is discarded (step S8). If the result of the check is“PASS”, it is determined whether or not all the tests using the timeinterval “t1” have been finished (step S7). If the result of thedetermination is “NO”, the procedure returns to the step S5.

Subsequently, the steps S5 to S7 are repeated until the result of thedetermination of whether or not all the tests have been finished is“YES”.

If the result of the determination is “YES”, the test mode selectionsignal TS is switched from L to H to raise the second operation modeswitch signal TE2 to H. The third switching circuit (MUX3) 43 is thusset to select the second testing refresh pulse signal TREF2, outputtedby the second testing refresh pulse generating circuit 64 (step S9).

Then, as in the case of Embodiment 1 (2), a read address is set (S10)and the memory is checked (S11). If the result of the check is “NG”, thetest is ended and the chip is discarded (step S13). If the result of thecheck is “PASS”, it is determined whether or not all the tests using thetime interval “t2” have been finished (step S12). If the result of thedetermination is “NO”, the procedure returns to the step S10.

Subsequently, the steps S10 to S12 are repeated until the result of thedetermination of whether or not all the tests have been finished is“YES”.

As described above, the third embodiment of the present invention canproduce the effects of both first and second embodiments. Specifically,tests can be carried out under both first and second worst timingconditions; the first worst timing condition may be set by generatingthe first testing refresh pulse signal TREF1 the predetermined time(TA1′) after the address transition detection signal ATD has beenchanged and setting the self refresh operation to be started so as tominimize the time interval “t1” between the self refresh operation andthe preceding read or write operation, and the second worst timingcondition may be set by generating the second testing refresh pulsesignal TREF2 the predetermined time (TA2′) after the address transitiondetection signal ATD has been changed and setting the self refreshoperation to be started so as to minimize the time interval “t2” betweenthe self refresh operation and the preceding read or write operation.

Fourth Embodiment

A fourth embodiment of the present invention will be described belowwith reference to the drawings.

In the first to third embodiments, the time interval between the writeor read operation and the self refresh operation is focused on to carryout tests by forcedly generating the worst timing condition. However, inthe present embodiment, not only the time interval (timing) but also therelationship between the row address for the read or write operation andthe row address for the self refresh operation are focused on to carryout tests by forcedly generating the worst timing condition.

Thus, a semiconductor memory device according to the present embodimentdiffers from the first, second, and third embodiments in that anexternally inputted row address is used for the refresh operation in thetest mode. The circuit configuration of the present semiconductor memorydevice can be accomplished by partly changing the circuit configurationshown in FIG. 1 or 6. However, in the present embodiment, the case inwhich the circuit configuration shown in FIG. 6 is partly changed willbe described by way of example.

FIG. 9 is a block diagram showing the configuration of the semiconductormemory device according to the present embodiment. This configurationdiffers from the circuit configuration shown in FIG. 6 in that a datastore circuit 70 and a fourth switching circuit (MUX4) 44 areadditionally provided. The test mode entry circuit 53 receives the modeentry signal TE as an input to output and supply the first operationmode switch signal TE1 to the first switching circuit (MUX1) 41.Furthermore, the test mode entry circuit 53 receives the test modeselection signal TS as an input to output and supply the secondoperation mode switch signal TE2 to the third switching circuit (MUX3)43. Moreover, the test mode entry circuit 53 receives the test modeselection signal TA as an input to output and supply the third operationmode switch signal TE3 to the data store circuit 70, while outputtingand supplying a fourth operation mode switch signal TE4 to the fourthswitching circuit (MUX4) 44.

Description will be given of a normal operation performed by thesemiconductor memory device according to the present embodiment. In thenormal operation mode, the test mode entry signal TE is set to L, andthe first operation mode switch signal TE1=L. Accordingly, the firstswitching circuit (MUX1) 41 is set to select the normal refreshing pulsesignal REF, generated by the refresh pulse generating circuit 60.Further, the test mode selection signal TA is set to H, the thirdoperation mode switch signal TE3=L, and the fourth operation mode switchsignal TE4=L. Accordingly, the data store circuit 70 is set to avoidloading the row address data AddR. Further, the fourth switching circuit(MUX4) 44 is set to deselect the testing row address data TAdd from thedata store circuit 70, while selecting an internal refresh address CAddgenerated by the refresh address generating circuit 66.

Accordingly, as in the case of the normal operation described in thefirst embodiment, in the normal operation mode, the read/write operationis performed on the basis of the timing for a change in the status ofthe externally inputted read/write address signal Add and addresstransition detection signal ATD. The refresh operation is performed onthe basis of the timing for the normal refreshing pulse signal REF,generated by the internal refresh pulse generating circuit 60, and theinternal refresh address CAdd, generated by the refresh addressgenerating circuit 66.

Next, the test mode operation will be described. The test mode operationincludes the test operation performed under the first worst timingcondition and the test operation performed under the second worst timingcondition, as described in the Embodiment 3. FIG. 10 is a timing chartillustrating the test operation performed under the first worst timingcondition. FIG. 11 is a timing chart illustrating the test operationperformed under the second worst timing condition. First, with referenceto FIG. 10, description will be given of the test operation performedunder the first worst timing condition. Subsequently, with reference toFIG. 11, description will be given of the test operation performed underthe second worst timing condition.

As shown in FIG. 10, at a time T70, the test mode entry signal TE is setto H. and the test entry circuit 53 enters the test mode. Subsequently,the signal TE2 generated from the inputted first test mode selectionsignal TS=L is recognized as an operation mode switch signal andsupplied to the third switching circuit (MUX3) 43. Then at a time T71,the second test mode selection signal TA falls to L. The test entrycircuit 53 senses this fall to raise the third operation mode switchsignal TE3 to H. In response to a rise in the third operation modeswitch signal TE3, the data store circuit 70 loads row address data AddR“A0” externally inputted via the address buffer circuit 21. The datastore circuit 70 then supplies the address data “A0” to the fourthswitching circuit (MUX4) 44 as the testing row address data TAdd.

At a time T73, the test mode selection signal TA rises to H. The testentry circuit 53 senses this rise to raise the fourth operation modeswitch signal TE4 to H. In response to a rise in the fourth operationmode switch signal TE4, the fourth switching circuit (MUX4) 44 is set todeselect refresh address CAdd “R0” generated by the refresh addressgenerating circuit 66, while selecting testing row address data TAdd“A0” outputted by the data store circuit 70. The testing row addressdata TAdd “A0” is supplied to the second switching circuit (MUX2) 42 asrefresh address RAdd “A0” (time T74).

At a time T75, the externally inputted read/write address signal Addchanges from “A0” to “A1”. The address transition detection circuit (ATDcircuit) 25 senses the change in address to raise the address transitiondetection signal ATD at a time T76. The address transition detectioncircuit (ATD circuit) 25 supplies the address transition detectionsignal ATD to the row control circuit 26 as a positive one shot pulsesignal. Then, the read or write operation is performed on the memorycell specified by the address A0 as in the case of Embodiments 1 to 3.

Now, the self refresh operation in the test mode will be described. Theself refresh operation is activated in association with an externallyinputted signal on the basis of internally generated timings andaddresses.

The first testing refresh pulse generating circuit 62 detects a fallingedge of the address transition detection signal ATD at the time T78. Thepredetermined time (TA1′) after the time T78, the first testing refreshpulse generating circuit 62 generates the first testing refresh pulsesignal TREF1 as a one shot pulse signal having a pulse widthcorresponding to the time required for one refresh operation. Aspreviously described, the pulse width of the first testing refresh pulsesignal TREF1 is set to be the same as that of the normal refreshingpulse signal REF.

Accordingly, the first testing refresh pulse signal TREF1 is supplied tothe first switching circuit (MUX1) 41 via the third switching circuit(MUX3) 43. Thus at a time T81, the first testing refresh pulse signalTREF1 is supplied to the second switching circuit (MUX2) 42 as therefresh timing control signal RF having the same pulse width as that ofthe normal refreshing pulse signal REF.

The fourth switching circuit (MUX4) 44 has selected the testing rowaddress data TAdd, supplied by the data store circuit 70. Accordingly,the testing row address data TAdd “A0” has already been supplied to thesecond switching circuit (MUX2) 42 as the refresh address RAdd “A0”. Thesecond switching circuit (MUX2) 42 uses a rise in the refresh timingcontrol signal RF at a time T81 as a trigger to deselect row addressdata AddR=A1, while selecting the refresh address RAdd “A0”. At a timeT82, the row address MAdd switches from “A1” to “A0”.

Furthermore, in response to the rise in the refresh timing controlsignal RF at the time T81, the second switching circuit (MUX2) 42 raisesthe row enable signal RE (not shown) and supplies the row decode circuit31 with the row enable signal having a predetermined pulse width. Sincethe second switching circuit (MUX2) 42 has already inputted the refreshaddress MAdd=A0 to the row decode circuit 31, the word line Wordspecified by the address TAdd=A0 to refresh the memory cell at a timeT79.

Subsequently at a time T84, the refresh timing control signal RF falls.Then, the second switching circuit (MUX2) 42 determines that the selfrefresh operation has been finished. The second switching circuit (MUX2)42 thus switches the row address MAdd from TAdd=A0 to the row addressdata AddR (A1).

As in the case of the first and third embodiments, the predeterminedtime (TA1) is based on the total time of the pulse width of thespecified word line, corresponding to the time between the time T79 andthe time T80, and the time interval “t1”, corresponding to the timebetween the time T80 and the time T83, as well as the delay time betweenthe signals. Accordingly, tests can be carried out by forcedlygenerating a condition that the time interval between the read or writeoperation and the self refresh operation has the smallest value possiblefor the circuit configuration.

Now, with reference to FIG. 11, description will be given of the testoperation performed under the second worst timing condition. The processbetween the entry into the test mode (T85) and the loading of thetesting row address data TAdd “A0” (T89) is the same as that of the testoperation performed under the first worst timing condition.

At a time T90, the read/write address signal Add changes from “A0” to“A1”. The address transition detection circuit (ATD circuit) 25 sensesthe change in address to raise the address transition detection signalATD at a time T91. The address transition detection circuit (ATDcircuit) 25 supplies the address transition detection signal ATD to therow control circuit 26 as a positive one shot pulse signal.

Furthermore, the second testing refresh pulse generating circuit 64detects a rising edge of the address transition detection signal ATD atthe time T91. The predetermined time (TA2′) after the time T91, thesecond testing refresh pulse generating circuit 64 generates the secondtesting refresh pulse signal TREF2 as a one shot pulse signal having apulse width corresponding to the time required for one refreshoperation.

The second testing refresh pulse signal TREF2 is supplied to the firstswitching circuit (MUX1) 41 via the third switching circuit (MUX3) 43.Thus at a time T92, the second testing refresh pulse signal TREF2 issupplied to the second switching circuit (MUX2) 42 as the refresh timingcontrol signal RF having the same pulse width as that of the normalrefreshing pulse signal REF.

In response to a rise in the refresh timing control signal RF at thetime T92, the second switching circuit (MUX2) 42 determines that therefresh operation has been activated. The second switching circuit(MUX2) 42 then selects the testing row address data TAdd=A0, outputtedby the data store circuit 70 and supplied via the fourth switchingcircuit (MUX4) 44 as the refresh address RAdd. Thus, the row addressMAdd is switched to A0.

Furthermore, in response to the rise in the refresh timing controlsignal RF at the time T92, the second switching circuit (MUX2) 42 raisesthe row enable signal RE (not shown) and supplies it to the row decodecircuit 31. Since the second switching circuit (MUX2) 42 has alreadyinputted the row address MAdd to the row decode circuit 31, the wordline Word specified by the row address MAdd (TAdd=A0) is activated.

Then, the memory cell specified by the testing row address TAdd (A0) isrefreshed as in the case of Embodiments 1 to 3.

Then, a falling edge of the address transition detection signal ATD at atime T98 is used as a trigger to raise and supply the row enable signalRE to the row decode circuit 31. Since the second switching circuit(MUX2) 42 has already inputted the refresh address MAdd to the rowdecode circuit 31, the word line Word specified by the row address MAdd(AddR=A1) is activated at T99. Thereafter, the read and write operationis performed as in the case of Embodiments 1 to 3.

As in the case of Embodiments 2 and 3, the time from the rise in theaddress transition detection signal ATD at the time T91 to the rise inthe word line for the read or write operation at the time T99 is basedon the sum of the predetermined time (TA2), the pulse width in the selfrefresh operation, corresponding to the time between the time T94 andthe time T96, and the shortest time interval possible for the circuitconfiguration, denoted by “t2”, as well as the delay time between thesignals.

Therefore, it is possible to carry out tests by forcedly generating acondition that the time interval between the self refresh operation andthe read or write operation has the smallest value “t2” possible for thecircuit configuration.

As described above, in the test mode, not only the read or writeoperation but also the self refresh operation are performed on the basisof the externally inputted refresh address. Consequently, therelationship of the row address between the read or write operation andthe self refresh operation can be arbitrarily controlled externally.Specifically, the read or write address “A1” in FIGS. 3 and 5 andrefresh address “R0” can be arbitrarily controlled externally.

The operation of the semiconductor memory device according to thepresent embodiment is different from the operation of the semiconductormemory device according to the third embodiment mainly in that the selfrefresh operation in the test mode is performed on the basis of thetesting refresh address TAdd, externally inputted and supplied via thedata store circuit 70, that is, the externally inputted refresh address.Accordingly, by setting, as the relationship between the read or writeaddress “A1” and the refresh address “A0”, the worst address condition,for example, a row address specifying two adjacent word lines, tests canbe carried under the worst timing condition but also under the worstaddress condition.

Subsequently, with reference to the flow chart in FIG. 12, descriptionwill be given of a procedure to test the semiconductor memory device. Inthe description below, tests are first conducted under the first worsttiming condition and then under the second worst timing condition.

First, a hold test (S1) and a memory write (S2) are carried out as inthe case of Embodiments 1 and 2. Then, the test mode is entered underthe first worst timing condition as in the case of Embodiment 3 (S4).

Then, the address signal TA is switched from H to L, and the thirdoperation mode switch signal TE3 is raised to H.. The data store circuit70 then loads the row address AddR (testing refresh address data),outputted by the address buffer circuit 21. The data store circuit 70then supplies the row address AddR to the fourth switching circuit(MUX4) 44 as the testing row address data TAdd (step S5).

Then, an arbitrary read/write address signal Add is applied to theaddress terminal (step S6).

The above process performs a read or write operation with the rowaddress “A1” shown in FIG. 3, and at the minimum time interval “t1”later, performs a self refresh operation with the row address “R0”.

Then, data is read from the memory cell connected to the word linespecified by the above address and is then checked (step S7). If theresult of the check is “NG”, the tests are ended and the chip isdiscarded (step S9). On the other hand, if the result of the check is“PASS”, it is determined whether or not all the tests have been finished(step S8). If the result of the determination is “NO”, the procedurereturns to the step S5.

Subsequently, the steps S5 to S8 are repeated until the result of thedetermination of whether or not all the tests have been finished is“YES”.

If the result of the determination is “YES”, then the test modeselection signal TS is switched from L to H and the second operationmode switch signal TE2 is raised to H. The third switching circuit(MUX3) 43 is then set to select the second testing refresh pulse signalTREF2, outputted by the second testing refresh pulse generating circuit64.

Then, as in the case of the step S5, the testing refresh address dataAddR is supplied to the fourth switching circuit (MUX4) 44 as thetesting row address data TAdd (step S11).

Then, an arbitrary read/write address signal Add is applied to theaddress terminal (step S12).

The above process performs a self refresh operation with the row address“R0” shown in FIG. 5, and at the minimum time interval “t2” later,performs a read or write operation with the row address “A1”.

Then, data is read from the memory cell connected to the word linespecified by the above address and is then checked (step S13). If theresult of the check is “NG”, the tests are ended and the chip isdiscarded (step S15). On the other hand, if the result of the check is“PASS”, it is determined whether or not all the tests have been finished(step S14). If the result of the determination is “NO”, the procedurereturns to the step S11.

Subsequently, the steps S11 to S14 are repeated until the result of thedetermination of whether or not all the tests have been finished is“YES”.

As described above, the fourth embodiment according to the presentinvention produces the same effects as those of the first to thirdembodiments. Furthermore, according to the fourth embodiment, the testscan be carried out by forcedly generating the worst address conditionalso taking into account the relationship between the row address forthe read or write operation and the row address for the self refreshoperation. That is, the tests can be carried out by forcedly generatingnot only the worst timing condition but also the worst addresscondition.

Fifth Embodiment

A fifth embodiment of the present invention will be described below withreference to the drawings. FIG. 13 is a block diagram showing theconfiguration of a semiconductor memory device according to the fifthembodiment. FIG. 14 is a timing chart showing a test operationperformed, under the first worst condition, by the semiconductor memorydevice shown in FIG. 13. FIG. 15 is a timing chart showing a testoperation performed, under the second worst condition, by thesemiconductor memory device shown in FIG. 13.

According to the first to fourth embodiments, when the timing for therefresh operation in the test mode is determined, a testing refreshpulse is generated using as a trigger a signal indicating that a changein an externally inputted address has been detected, that is, theaddress transition detection signal generated by the address transitiondetecting circuit (ATD circuit) 25. This enables a read or writeoperation and a refresh operation to be generated by force temporallyclose to each other.

However, some pseudo SRAMs generate an ATD signal depending on a changeof the address as well as an externally inputted signal that selectivelyactivates a selected area of a chip, a bank, or the like, for example, achip select signal. The input of the chip select signal /CS does notnecessarily synchronize with the timing signal TM, generated by theinternal timer circuit 50. Consequently, it may be necessary to test thetime interval between a refresh operation in the normal operation modeand a read or write operation based on a timing for activating the chipselect signal /CS.

In the description of the first to fourth embodiments, the chip selectsignal /CS is premised to be active. However, in the description below,it is premised that the addresses are not changed but that the chipselect signal /CS shifts from an inactive status to an active status.The semiconductor memory device according to the present embodiment isset to be inactive when /CS=1 and to be active when /CS=L. With a fallin the signal /CS, the address transition detecting circuit (ATDcircuit) 25 generates an address transition detection signal ATD. Theaddress transition detection signal ATD is then used as a trigger tocarry out tests under the first and second worst timing conditions.

Now, the test mode operation will be described. The test mode operationincludes a test operation performed under the first worst timingcondition and a test operation performed under the second worst timingcondition as previously described. FIG. 14 is a timing chartillustrating the test operation performed under the first worst timingcondition. FIG. 15 is a timing chart illustrating the test operationperformed under the second worst timing condition.

Embodiment 5 is the same as Embodiments 1 to 4 except that an addresstransition detection signal ATD is generated in response to a fall inthe signal /CS (from inactive status to active status).

Specifically, in the test operation performed under the first worsttiming condition as shown in FIG. 14, an address transition detectionsignal ATD is generated in response to a fall in the signal /CS (T103).Then, as in the case of Embodiments 1 to 4, a read or write operation isperformed on the memory cell specified by the address A0, and thepredetermined time interval t1 later, a refresh operation is performedon the word line specified by the address A1. The example of a testoperation shown in FIG. 14 uses an externally inputted refresh address(Embodiment 4). Accordingly, the entry into the test mode (T101), theloading of the refresh address, and the like are carried out using thesame procedure as that of Embodiment 4 as shown in FIG. 14.

The test operation performed under the second worst timing condition asshown in FIG. 15 is also similar to that in Embodiments 1 to 4 exceptthat an address transition detection signal ATD is generated in responseto a fall in the signal /CS (T105). A read or write operation isperformed on the memory cell specified by the address A0, and thepredetermined time interval t2 later, a refresh operation is performedon the word line specified by the address A2. The entry into the testmode (T104), the loading of the refresh address, and the like arecarried out using the same procedure as that of Embodiment 4 as shown inFIG. 14.

Moreover, the first to fifth embodiments show the example in which thetest circuit operating in the test mode is built into the semiconductormemory device. However, the whole circuit of a semiconductor memorydevice which is composed of a memory cell array and a peripheral circuitmay be mounted on a single chip or the whole circuit may be divided intoseveral functional blocks that are mounted on separate chips asrequired. In the latter case, a mixed IC may be provided; the memorycell array and the peripheral circuit may be mounted on separate chipswhich are sealed in a single package. That is, the scope of the presentinvention includes the configuration in which a control chip providedoutside a memory chip supplies various control signals to the memorychip.

Further, the present invention is not limited to the configurations ofthe above embodiments. Many variations may be made to theseconfigurations without departing from the spirit of the presentinvention.

INDUSTRIAL APPLICABILITY

To ensure that even if a read or write operation and a self refreshoperation of a semiconductor memory device which are independent of eachother are generated temporally close to each other, the operations areprevented from interfering with each other to cause malfunction, thepresent invention enables operations of the semiconductor memory deviceto be checked by providing the device with a predetermined time intervaland operating it using this time interval to confirm that malfunction isavoided.

Further, tests are carried out by forcedly generating the worst addresscondition taking into consideration of relationship between a rowaddress for the read or write operation and the row address for the selfrefresh operation. This enables the tests to be carried out bygenerating not only the worst timing condition but also the worstaddress condition.

1-4. (canceled)
 5. A semiconductor memory device, comprising: aplurality of memory cells to be refreshed: an access control circuitthat accesses a memory cell corresponding to an input address signal toexecute a read or a write: and a refresh control circuit that carriesout, in a normal operation mode, refreshing using a refresh timinggenerated independently of the access operation, and that carries out,in a test mode, refreshing using a refresh timing generated in responseto the access operation, wherein in the test mode, the refresh controlcircuit controls the refresh timing so that the refreshing is started apredetermined time after the access has been completed. 6-7. (canceled)8. A semiconductor memory device, comprising: a plurality of memorycells to be refreshed; an address transition detecting circuit thatgenerates an address transition detection signal in response to an inputaddress signal; a refresh timing generating circuit which generates anormal-operation refresh timing signal independent of the addresstransition detection signal, in a normal operation mode, and whichgenerates a testing refresh timing signal in response to the addresstransition detection signal in a test mode; and a refresh addressgenerating circuit that generates a refresh address on the basis of thenormal-operation refresh timing signal or the testing refresh timingsignal.
 9. A semiconductor memory device as claimed in claim 8, furtherincluding: a memory cell control circuit which accesses a memory cellcorresponding to the input address signal in response to the addresstransition detection signal to execute a read or a write and whichcarries out refreshing in response to an output signal from the refreshtiming generating circuit, and wherein in the test mode, the refreshtiming generating circuit generates the testing refresh timing signal sothat in response to the change in the input address signal, the accessand the refreshing are carried out with a predetermined time interval.10. A semiconductor memory device as claimed in claim 9, wherein thetesting refresh timing signal is set to start the refreshing thepredetermined time after the access has been completed.
 11. Asemiconductor memory device as claimed in claim 8, wherein the testingrefresh timing signal is set to start the access the predetermined timeafter the refreshing has been completed.
 12. A semiconductor memorydevice as claimed in claim 8, wherein either the normal operation modeor the test mode is set in response to an inputted test mode entrysignal.
 13. A semiconductor memory device as claimed in claim 12,further including a refresh timing switching circuit that selects eitherthe normal-operation refresh timing signal or the testing refresh timingsignal to supply the selected timing signal to the memory cell controlcircuit, in response to the test mode entry signal.
 14. A semiconductormemory device as claimed in claim 13, further including an addressswitching circuit that selects either the input address signal or therefresh address signal to supply the selected address signal to thememory cell circuit, in response to an output signal from the refreshtiming switching circuit.
 15. A semiconductor memory device as claimedin claim 9, wherein the refresh timing generating circuit generates: afirst testing refresh timing signal set to start the refreshing a firstpredetermined time after the access to the memory cell has beencompleted, and a second testing refresh timing signal set to start theaccess a second predetermined time after the refreshing has beencompleted.
 16. A semiconductor memory device as claimed in claim 15,further including: a testing refresh timing switching circuit thatselects either the first testing refresh timing signal or the secondtesting refresh timing signal to supply the selected timing signal to arefresh timing switching circuit, in response to an inputted testingrefresh timing select signal.
 17. A semiconductor memory device asclaimed in claim 14, wherein the refresh address signal is internallygenerated.
 18. A semiconductor memory device as claimed in claim 14,further including a testing refresh address switching circuit thatselects either the internally generated address signal or the externallyinputted address signal to supply the selected address signal to theaddress switching circuit, in response to an inputted testing refreshaddress select signal.
 19. A semiconductor memory device as claimed inclaim 8, wherein the normal-operation refresh timing signal is generatedon the basis of an output signal from a timer circuit operatingindependently of the address transition detection signal.
 20. Asemiconductor memory device as claimed in claim 8, wherein the addresstransition detection signal is generated in response to a change in anactivation control signal which switches the semiconductor memory devicefrom an inactive status to an active status. 21-22. (canceled)
 23. Atest circuit, comprising: a refresh timing generating circuit thatgenerates a normal-operation refresh timing independent of an access toa memory cell corresponding to an input address signal, and a testingrefresh timing responding to the access to the memory cell; and arefresh timing switching circuit that selects and outputs either thenormal-operation refresh timing signal or the testing refresh timingsignal in response to an inputted test mode entry signal, wherein thetesting refresh timing is set so that the refreshing is started apredetermined time after the access has been completed.
 24. (canceled)25. A test circuit, comprising: a refresh timing generating circuit thatgenerates a normal-operation refresh timing independent of an access toa memory cell corresponding to an input address signal, and a testingrefresh timing responding to the access to the memory cell; a refreshtiming switching circuit that selects and outputs either thenormal-operation refresh timing signal or the testing refresh timingsignal in response to an inputted test mode entry signal; and a testingrefresh address switching circuit that selects and outputs either aninternally generated address signal or an externally inputted addresssignal in response to an inputted testing refresh address select signal.26. (canceled)
 27. A method of testing a semiconductor memory device,having a plurality of memory cells to be refreshed, the methodcomprising: a step of writing a predetermined test pattern in the memorycells: a step of deselecting a refresh timing independent of an accessto a memory cell corresponding to an input address signal and selectinga refresh timing responding to the access; a step of carrying out theaccess and refreshing corresponding to the access with a preset timeinterval; a step of checking data read from the memory cell against thetest pattern to determine whether or not the semiconductor device isacceptable; and a step of using an externally inputted address signal tospecify a word line to be refreshed. 28-31. (canceled)
 32. Asemiconductor memory device, comprising: a plurality of memory cells tobe refreshed; an address transition detecting circuit that generates anaddress transition detection signal in response to a change in anexternal address; a timer circuit that outputs timing signals at fixedtime intervals; a refresh pulse generating circuit that generates andoutputs a normal refreshing pulse signal on the basis of the timingsignal; a first testing refresh pulse generating circuit that generatesand outputs a first testing refresh pulse signal on the basis of theaddress transition detection signal; a first switching circuit thatreceives at least the normal refreshing pulse signal and the firsttesting refresh pulse signal to selectively output them on the basis ofa test mode entry signal; a refresh address generating circuit thatoutputs a refresh address in response to the output of the firstswitching circuit; and a second switching circuit that selects andoutputs either a part of the external address or a part of the refreshaddress in response to the output of the first switching circuit, theoutput from the second switching circuit selecting a row of the memorycell array.
 33. A semiconductor memory device as claimed in claim 32,wherein a period in which the address transition detection signal isactivated does not overlap a period in which the output signal from thefirst switching circuit is activated.
 34. A semiconductor memory deviceas claimed in claim 32, wherein a period in which the address transitiondetection signal is activated overlaps a period in which the outputsignal from the first switching circuit is activated.
 35. Asemiconductor memory device as claimed in claim 32, further including: asecond testing refresh pulse generating circuit that generates andoutputs a second testing refresh pulse signal, having a timing differentfrom that of the first testing refresh pulse signal, on the basis of theaddress transition detection signal, wherein the first selecting circuitfurther receives the second testing fresh pulse signal to selectivelyoutput the normal refreshing pulse signal and the first and secondtesting refresh pulse signal on the basis of the test entry signal. 36.A semiconductor memory device as claimed in claim 35, wherein a periodin which the output signal from the first switching circuit is activatedoverlaps a period in which the address transition detection signal isactivated, in association with the second testing refresh pulse signal,and wherein the period in which the output signal from the firstswitching circuit is activated does not overlap the period in which theaddress transition detection signal is activated, in association withthe first testing refresh pulse signal.